One way to improve the performance of a computer system is the implementation of a Reduced Instruction Set (RISC) microprocessor. RISC microprocessors use a smaller instruction set than Complex Instruction Set (CISC) microprocessors. Because less hardware is required to implement a smaller instruction set, RISC instructions tend to be executed more quickly than CISC instructions.
However, because of an established base of CISC software, it is desirable to provide RISC microprocessors that are capable of executing CISC instructions to maintain compatibility with existing software. In order to execute CISC instructions, RISC microprocessors typically have one or more decoders that translate CISC macroinstructions into one or more RISC micro-operations prior to execution.
In order to more efficiently use microprocessor resources, some of the decoders may not be fully functional decoders capable of decoding any instruction in the CISC instruction set. For example, one or more of the decoders may be limited to decoding instructions that can be executed by a single-cycle RISC micro-operation. Alternatively, a decoder may only translate a subset of the CISC instructions that is used most often.
Because any decoder may receive an invalid opcode, each decoder must be capable of invoking an invalid opcode exception handler, whether or not the decoder is fully functional. However, if a decoder is limited to producing only one single-cycle micro-operation, a fault handler cannot be invoked directly because a fault handler typically requires more information than can be provided by a single-cycle micro-operation. Invocation of an exception handler typically requires the type of exception that was caused and the exception handler to be invoked.
Thus, it would be desirable to provide a method and apparatus for triggering invalid opcode exceptions with a single-cycle micro-operation, such as an event-signaling micro-operation.